General information

Education

I did M.Tech in Microelectonics from BITS Pilani, and B.Tech from SASTRA University, India.

Have around 5years industry experiance in VLSI Design from RTL to GDS, where I did, Micro-architectral Design, Synthesis, Timing constraints creation, UPF development, Static timing analysis, Placement and Routing, DFT Insertion and ATPG.

Have very good command on low power design and verification methods.

Experience: 5 years

About me

You will learn about :

1. What is RTL?

2. What is Timing constraints, UPF, Power constraints etc?

3. What is Synthesis?

4. Checks like MVRC/LEC etc

5. RTL to Netlist flow